1. Field
The present disclosure relates software tools used in computer aided design (CAD) of integrated circuits, and more specifically to a method and apparatus for validating integrated circuits for electro static discharge (ESD) compliance.
2. Related Art
Electro static discharge (ESD) generally refers to the flow of electric charges (current) through the interface pads of an integrated circuit (IC), typically while not in use. One example of such not-in-use scenario is while packages containing the ICs are transported/moved prior to deployment in corresponding systems/devices. A common reason for the ESD is interface pads coming in contact with human beings while being deployed on systems or during transportation.
ESD is generally undesirable in that the magnitude of the current is often much higher than the magnitude for which an IC may be designed for during normal use in systems/devices. Such high current flow can damage various functional circuits within an IC, as is well known in the relevant arts. Accordingly, there has been a general need to avoid ESD current flowing through the functional circuits within an IC, as is well known in the relevant arts.
Protection circuits are accordingly often implemented associated with the portions functional circuits and/or the pads to avoid the flow of ESD current through functional circuits (Aprotected circuits@). Validation of an IC for ESD compliance generally refers to ensuring adequate protection circuit for each portion of a functional circuit that may be susceptible to ESD discharge noted above. Such portions often provide path from a interface pad to Vdd (supply terminal) or ground.
The validation generally needs to be efficiently integrated into the design approach employed to design ICs. In one approach, an IC designer may generate a schematic circuit graphically representing electronic/electrical components (e.g., transistors, diodes, capacitors) and their connectivity in a schematic phase. The netlist (textual representation of the graphic information) resulting from the schematic phase may be used by a routing and placement phase to place the components meeting various criteria. Further checks may be performed to ensure that the eventually fabricated circuit meets various criteria.
In general, the ESD compliance validation needs to be performed within the context of at least such a design approach, while meeting one or more requirements such as reduced time to complete design (prior to fabrication), simplicity, reduced effort, etc.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.